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The presentation will discuss the future memory technologies beyond the 30 nm node, especially for DRAM, NAND Flash, new memories such as Phase change RAM (PRAM), and ferroelectric RAM (FRAM), and novel device structure technologies, which include how far we can extend so far successful conventional semiconductor memories. First of all, business demands and new applications of memories will be summarized...
MOSFET scaling has served our industry well for several decades by providing significant improvements in performance, density and power, but traditional MOSFET scaling has run into hard roadblocks. Interconnect and patterning technologies have also run into significant limitations when trying to follow traditional scaling methods. The past few years have seen the introduction of new materials and...
IC power consumption is not only a package thermal issue but also a significant and fast growing part of the world electricity consumption. A new low voltage transistor could contribute greatly to the need for a new Vdd scaling scenario. Green transistor (gFET) is based on tunneling and provides Ion and Ioff far superior to MOSFET at 0.2V if suitable low-Eg material is introduced into IC manufacturing.
In this paper, experimental studies on the carrier transport in silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is proposed, which takes into account...
The Impact Ionization MOS (IMOS) transistor is a kind of promising concept as a candidate of MOS transistor due to its abrupt switching. However, some key issues will limit IMOS transistors for practical applications. In this paper, detailed physical explanations for the non-saturation of IMOS output characteristics and the unanticipated low drive current are presented. A new method to enhance the...
In this paper, focused on especial requirement of monolithic power IC, a BCD compatible technology was studied and built up by solving a series of key technical issues. Using the BCD process, NPN, N-type VDMOS, PMOS, NMOS devices are obtained. For NPN transistor, BVCEO is 25 V and ?? is 50, for N-type VDMOS transistor, BVDS is 35 V and VT is 2.5 V, for PMOS transistor, BVDS is 15 V, and VT is -1.5...
A charge based compact model with self-heating effects has been developed for LDMOS transistors. Both the channel and drift regions in LDMOS are modeled without adding an internal drain node. An efficient scheme for including self-heating effects is implemented in the model, which requires no thermal network. A comparison with measured data from an LDMOS shows that the model has excellent accuracy...
Accurate prediction of circuit aging and its variability is essential to reliable design and analysis. Such a capability further helps reduce the load in statistical reliability test. Based on the physical understanding of circuit aging effects, we develop a predictive short term and long term model to characterize NBTI-induced threshold voltage degradation (??Vth) at transistor level. Due to process...
Critical currents (ICRIT) extracted from the N-curves of a 6-T SRAM bit cell have been shown in recent research to be important and effective figures of merit for the cell??s stability and write-ability. SPICE models of cell transistors, therefore, not only need to fit closely to individual transistor??s I-V characteristics, but also faithfully reproduce ICRITs?? behavior of the cell as a whole. A...
This paper presents the fundamentals and recent progresses of 4-port based error correction and parasitics de-embedding techniques we developed for high frequency transistor measurements. RF CMOS data from 2 to 110 GHz will be shown to illustrate various techniques.
This article summarizes the history and progresses on our development of the Bipolar Field-Effect Transistor Theory (BiFET). The 2-Dimensional (2-D) rectangular geometry of the transistor (uniform in the width or Z-direction) is employed to decompose the 2-D equation into two 1-D equations which are parametrically coupled by the surface-electric-potential. This decomposition enables us to obtain the...
Carbon nanotubes (CNTs) are novel quasi-one-dimensional materials with excellent electrical properties in addition to their remarkable mechanical strength, thermal conductivity and chemical inertness. Moreover, semiconducting CNTs are direct-gap semi-conductors that directly absorb and emit light. This offers the possibility of developing a CNT-based electric and optoelectronic technology.
We report on the experimental evidence of a fully ballistic nano-FET with a voltage gain higher than 1 which is based on a 1D quantum ballistic conductor. In such a FET, the transconductance and the output conductance are basically modulated by the 1D subbands and the experimental results can theoretically be explained based on the Landauer-Buttiker formalism and the Buttiker model of the saddle-point...
As CMOS scaling continuous successfully, technologies for integrating both memory and logic together is highly desirable for high performance and low-power system-on-chip (SOC) with full CMOS compatibility, such as Logic based NVM, floating-body DRAM, MiM based eDRAM, PC-RAM, RRAM, MRAM, FeRAM, ...etc.. New materials (e.g. GST, metal-oxide, high-k, magnetic junction, ...etc.) have greater compatibility...
A capacitor-less DRAM cell based on ferroelectric-gate memory transistor structure is introduced. Compared to the conventional DRAM cell, it offers much simpler cell structure, longer retention time, easier scaling, and lower power consumption. Cell size of 4F2 can be realized. It is also most suitable for embedded applications.
The author invented a trench-capacitor dynamic-random-access memory (DRAM) cell and applied the Japanese patent in 1975. The first trial development of trench-capacitor DRAM cell was presented in 1982 in 1-Mbit DRAM era. This might be the first attempt to utilize vertical wall of silicon substrate for metal-oxide-semiconductor (MOS) structure. Subsequent to this trial various kinds of vertical-channel...
To help overcome limits to the density and speed of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM...
Enhanced flash memory device characteristics using ALD TiN/Al2O3 nanolaminate charge storage layers have been investigated. After annealing treatment, the TiN nanocrystals embedded in Al2O3 films with a small diameter of ~3 nm and a high-density of >1??1012/cm2 have been formed. The memory devices show a high programming speed of ??Vt >1 V@Vg/Vd=8 V/8 V, 10 ??s and an erasing speed of ??Vt >1...
In this paper, we present the investigation of inverse narrow width effect (INWE) of 65 nm low-power process with dual gate oxide shapes. To evaluate the impact of STI process on narrow devices, we conducted different experiments in STI process steps, including STI liner, STI elevation, STI liner annealing and STI nitride pullback. The result shows only STI liner annealing and STI nitride pullback...
If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance enhancements could induce high SRAM standby current and single cell failures in SRAM. In order to optimize the yield of eSiGe process, a SRAM-layout-based test structure was identified. It has the advantage of being able to be tested after silicidation or first metal level, therefore can be used as an early...
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